Staff Engineer, ASIC Design Verification
$163,000 – $253,000 USD
Tech Stack
Solid badges = required, outlined = preferred
Responsibilities
- Participate in verification strategy and methodology definitions.
- Contribute to micro architecture specification and reviews.
- Responsible for the verification of modules/subsystems of AI accelerators.
- Architect test benches, create test plans, implement test bench components in UVM.
- Work closely with architects and design engineers to define verification requirements and close functional and code coverage targets.
Soft Skills
Computation In MemoryAI Llm AcceleratorsWritten CommunicationVerbal CommunicationProblem SolvingCross-Functional Collaboration
Benefits
- 401k
- Charitable Giving Match
- Dental
- Flexible Hours
- Gym/Wellness
- Health Insurance
- Mental Health
- Paid Time Off
- Parental Leave
- Vision
Culture
Inclusive HiringTeam LeadershipMentorship ProgramLearning Budget
Requirements
Required: BE in Computer/Electrical Engineering or Computer Science
Preferred: MS in Computer/Electrical Engineering or Computer Science
Regions: Us
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About Samsung
Industry: semiconductor
Size: enterprise
Samsung's DRAM Development Lab (DDL), part of Samsung's Memory Business Unit, focuses on developing new technology for memory and storage to solve key problems in Cloud & Data centers. The SOC team within DDL specifically develops silicon solutions like Custom HBM base die and AI accelerators.
View company profile →Compensation
Base salary: $163,000 – $253,000 USD
Bonus: incentive opportunities that reward employees based on individual and company performance
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